System Settings

 
Environment Settings
Environment Variable xst ngdbuild map par
LD_LIBRARY_PATH /opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64:/usr/lib/jni /opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/lib/lin64:/opt/Xilinx/14.7/ISE_DS/EDK/lib/lin64:/opt/Xilinx/14.7/ISE_DS/common/lib/lin64:/usr/lib/jni /opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/lib/lin64:/opt/Xilinx/14.7/ISE_DS/EDK/lib/lin64:/opt/Xilinx/14.7/ISE_DS/common/lib/lin64:/usr/lib/jni < data not available >
PATH /opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/opt/microchip/xc32/v1.31/bin:/opt/microchip/xc16/v1.21/bin:/opt/microchip/xc32/v1.33/bin:/home/aldi/altera/13.0sp1/quartus/bin /opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:/opt/Xilinx/14.7/ISE_DS/common/bin/lin64:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/opt/microchip/xc32/v1.31/bin:/opt/microchip/xc16/v1.21/bin:/opt/microchip/xc32/v1.33/bin:/home/aldi/altera/13.0sp1/quartus/bin /opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:/opt/Xilinx/14.7/ISE_DS/common/bin/lin64:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/opt/microchip/xc32/v1.31/bin:/opt/microchip/xc16/v1.21/bin:/opt/microchip/xc32/v1.33/bin:/home/aldi/altera/13.0sp1/quartus/bin < data not available >
XILINX /opt/Xilinx/14.7/ISE_DS/ISE/ /opt/Xilinx/14.7/ISE_DS/ISE/ /opt/Xilinx/14.7/ISE_DS/ISE/ < data not available >
XILINX_DSP <  not set  > /opt/Xilinx/14.7/ISE_DS/ISE /opt/Xilinx/14.7/ISE_DS/ISE < data not available >
XILINX_EDK <  not set  > /opt/Xilinx/14.7/ISE_DS/EDK /opt/Xilinx/14.7/ISE_DS/EDK < data not available >
XILINX_PLANAHEAD <  not set  > /opt/Xilinx/14.7/ISE_DS/PlanAhead /opt/Xilinx/14.7/ISE_DS/PlanAhead < data not available >
 
Synthesis Property Settings
Switch Name Property Name Value Default Value
-ifn   cpu.prj  
-ofn   cpu  
-ofmt   NGC NGC
-p   xc7a100t-3-csg324  
-top   cpu  
-opt_mode Optimization Goal Speed Speed
-opt_level Optimization Effort 1 1
-power Power Reduction NO No
-iuc Use synthesis Constraints File NO No
-keep_hierarchy Keep Hierarchy No No
-netlist_hierarchy Netlist Hierarchy As_Optimized As_Optimized
-rtlview Generate RTL Schematic Yes No
-glob_opt Global Optimization Goal AllClockNets AllClockNets
-read_cores Read Cores YES Yes
-write_timing_constraints Write Timing Constraints NO No
-cross_clock_analysis Cross Clock Analysis NO No
-bus_delimiter Bus Delimiter <> <>
-slice_utilization_ratio Slice Utilization Ratio 100 100
-bram_utilization_ratio BRAM Utilization Ratio 100 100
-dsp_utilization_ratio DSP Utilization Ratio 100 100
-reduce_control_sets   Auto Auto
-fsm_extract   YES Yes
-fsm_encoding   Auto Auto
-safe_implementation   No No
-fsm_style   LUT LUT
-ram_extract   Yes Yes
-ram_style   Auto Auto
-rom_extract   Yes Yes
-shreg_extract   YES Yes
-rom_style   Auto Auto
-auto_bram_packing   NO No
-resource_sharing   YES Yes
-async_to_sync   NO No
-use_dsp48   Auto Auto
-iobuf   YES Yes
-max_fanout   100000 100000
-bufg   32 32
-register_duplication   YES Yes
-register_balancing   No No
-optimize_primitives   NO No
-use_clock_enable   Yes Auto
-use_sync_set   Yes Auto
-use_sync_reset   Yes Auto
-iob   Auto Auto
-equivalent_register_removal   YES Yes
-slice_utilization_ratio_maxmargin   5 0
 
Translation Property Settings
Switch Name Property Name Value Default Value
-intstyle   ise None
-dd   _ngo None
-p   xc7a100t-csg324-3 None
-uc   cpu.ucf None
 
Map Property Settings
Switch Name Property Name Value Default Value
-ol Place & Route Effort Level (Overall) high high
-xt Extra Cost Tables 0 0
-ir Use RLOC Constraints OFF OFF
-t Starting Placer Cost Table (1-100) Map 1 0
-r Register Ordering 4 4
-intstyle   ise None
-lc LUT Combining off off
-o   cpu_map.ncd None
-w   true false
-pr Pack I/O Registers/Latches into IOBs off off
-p   xc7a100t-csg324-3 None
 
Operating System Information
Operating System Information xst ngdbuild map par
CPU Architecture/Speed Intel(R) Core(TM)2 Duo CPU E7200 @ 2.53GHz/1603.000 MHz Intel(R) Core(TM)2 Duo CPU E7200 @ 2.53GHz/2533.000 MHz Intel(R) Core(TM)2 Duo CPU E7200 @ 2.53GHz/2533.000 MHz <  data not available  >
Host vlalex-PC vlalex-PC vlalex-PC <  data not available  >
OS Name Ubuntu Ubuntu Ubuntu <  data not available  >
OS Release Ubuntu 14.04.1 LTS Ubuntu 14.04.1 LTS Ubuntu 14.04.1 LTS <  data not available  >