cpu Project Status
Project File: schelet.xise Parser Errors: No Errors
Module Name: cpu Implementation State: Synthesized
Target Device: xc7a100t-3csg324
  • Errors:
 
Product Version:ISE 14.4
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary [-]
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentSun Nov 19 22:05:48 2017   
Translation ReportOut of DateSun Nov 19 22:05:47 2017   
Map ReportCurrentSun Nov 19 22:05:48 2017   
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogCurrentMon Nov 20 01:25:14 2017

Date Generated: 11/20/2017 - 23:23:08