cpu Project Status | |||
Project File: | schelet.xise | Parser Errors: | No Errors |
Module Name: | cpu | Implementation State: | Synthesized |
Target Device: | xc7a100t-3csg324 |
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Product Version: | ISE 14.4 |
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Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Device Utilization Summary | [-] |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Sun Nov 19 22:05:48 2017 | ||||
Translation Report | Out of Date | Sun Nov 19 22:05:47 2017 | ||||
Map Report | Current | Sun Nov 19 22:05:48 2017 | ||||
Place and Route Report | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
ISIM Simulator Log | Current | Mon Nov 20 01:25:14 2017 |