cpu Project Status (11/22/2014 - 21:33:33) | |||
Project File: | schelet.xise | Parser Errors: | No Errors |
Module Name: | gpio_sram | Implementation State: | Mapped (Failed) |
Target Device: | xc7a100t-3csg324 |
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Product Version: | ISE 14.7 |
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Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Device Utilization Summary | [-] |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | S nov. 22 14:13:00 2014 | ||||
Translation Report | Current | S nov. 22 14:13:27 2014 | ||||
Map Report | Current | S nov. 22 14:13:41 2014 | ||||
Place and Route Report | ||||||
CPLD Fitter Report (Text) | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
ISIM Simulator Log | Out of Date | S nov. 22 17:22:19 2014 | |
Post-Synthesis Simulation Model Report | Out of Date | J nov. 6 15:23:18 2014 |