cpu Project Status (11/22/2014 - 21:54:37) | |||
Project File: | schelet.xise | Parser Errors: | No Errors |
Module Name: | cpu | Implementation State: | Synthesized |
Target Device: | xc7a100t-3csg324 |
|
No Errors |
Product Version: | ISE 14.4 |
|
26 Warnings (26 new) |
Design Goal: | Balanced |
|
|
Design Strategy: | Xilinx Default (unlocked) |
|
|
Environment: | System Settings |
|
Device Utilization Summary | [-] |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Sun Nov 19 22:05:48 2017 | 0 | 26 Warnings (26 new) | 13 Infos (13 new) | |
Translation Report | Out of Date | Sun Nov 19 22:05:47 2017 | 0 | 0 | 0 | |
Map Report | Current | Sun Nov 19 22:05:48 2017 | X 2 Errors (2 new) | 2 Warnings (2 new) | 7 Infos (7 new) | |
Place and Route Report | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
ISIM Simulator Log | Current | Mon Nov 20 01:25:14 2017 | |
Post-Synthesis Simulation Model Report | Current | Sun Nov 19 22:05:49 2017 |