cpu Project Status (11/22/2014 - 21:54:37)
Project File: schelet.xise Parser Errors: No Errors
Module Name: cpu Implementation State: Synthesized
Target Device: xc7a100t-3csg324
  • Errors:
No Errors
Product Version:ISE 14.4
  • Warnings:
26 Warnings (26 new)
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary [-]
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentSun Nov 19 22:05:48 2017026 Warnings (26 new)13 Infos (13 new)
Translation ReportOut of DateSun Nov 19 22:05:47 2017000
Map ReportCurrentSun Nov 19 22:05:48 2017X 2 Errors (2 new)2 Warnings (2 new)7 Infos (7 new)
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogCurrentMon Nov 20 01:25:14 2017
Post-Synthesis Simulation Model ReportCurrentSun Nov 19 22:05:49 2017

Date Generated: 11/20/2017 - 01:32:36