l80soc Project Status (04/28/2012 - 12:00:22)
Project File:	xilinx_s3.xise	Parser Errors:	No Errors
Module Name:	l80soc	Implementation State:	Placed and Routed
Target Device:	xc3s200-4ft256	Errors:	No Errors
Product Version:	ISE 13.4	Warnings:	22 Warnings (0 new)
Design Goal:	Balanced	Routing Results:	All Signals Completely Routed
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:	All Constraints Met
Environment:	System Settings	Final Timing Score:	0  (Timing Report)

 

Device Utilization Summary					[-]
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	237	3,840	6%
Number of 4 input LUTs	384	3,840	10%
Number of occupied Slices	255	1,920	13%
Number of Slices containing only related logic	255	255	100%
Number of Slices containing unrelated logic	0	255	0%
Total Number of 4 input LUTs	385	3,840	10%
Number used as logic	368
Number used as a route-thru	1
Number used for Dual Port RAMs	16
Number of bonded IOBs	24	173	13%
Number of RAMB16s	3	12	25%
Number of BUFGMUXs	1	8	12%
Average Fanout of Non-Clock Nets	3.39

 

Performance Summary				[-]
Final Timing Score:	0 (Setup: 0, Hold: 0, Component Switching Limit: 0)	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	Sat 28. Apr 11:59:08 2012	0	22 Warnings (0 new)	7 Infos (1 new)
Translation Report	Current	Sat 28. Apr 11:59:29 2012	0	0	0
Map Report	Current	Sat 28. Apr 11:59:43 2012	0	0	4 Infos (0 new)
Place and Route Report	Current	Sat 28. Apr 12:00:08 2012	0	0	0
Power Report
Post-PAR Static Timing Report	Current	Sat 28. Apr 12:00:18 2012	0	0	5 Infos (0 new)
Bitgen Report

 

Secondary Reports			[-]
Report Name	Status	Generated

Date Generated: 04/28/2012 - 12:00:22