1. Adrian Nițu
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Adrian Nițu  committed b7dafaf
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lab5baseunclean

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    1. adriannitu92 Adrian Nițu
  • Parent commits 29b32e7
  • Branches lab5baseunclean
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Files changed (4)

File control_unit.v

View file 
     reg     [DATA_WIDTH-1:0] alu_out_buffer;
     reg     [DATA_WIDTH-1:0] writeback_value;
     wire    [ADDR_WIDTH-1:0] indirect_addr;
-    wire    [DATA_WIDTH-1:0] data_to_store;
+    reg     [DATA_WIDTH-1:0] data_to_store;
     reg     [DATA_WIDTH-1:0] sreg;
-
+    reg     [DATA_WIDTH-1:0] sp;
+    reg     [ADDR_WIDTH-1:0] saved_pc;
 `ifdef DEBUG
     assign debug_opcode_imd = opcode_imd;
     assign debug_writeback_value = writeback_value;
         .rd_we          (rd_we),
         .rr_oe          (rr_oe),
         .rd_oe          (rd_oe),
-        .opcode_rd        (opcode_rd),
-        .opcode_rr        (opcode_rr)
+        .opcode_rd      (opcode_rd),
+        .opcode_rr      (opcode_rr)
     );
 
     bus_interface_unit #(
         .indirect_addr(indirect_addr),
         .data_to_store(data_to_store)
     );
-     
-     assign indirect_addr =
+    
+
+    // TODO : indirect_addr hijack
+    // NU stricati functionalitatea curenta
+    assign indirect_addr =
         (opcode_group[`GROUP_LOAD_INDIRECT] ||
          opcode_group[`GROUP_STORE_INDIRECT]) ?
         // else, indirect to memory => X or Y or Z
                 {alu_rr, alu_rd} :
         // else, not indirect
             {ADDR_WIDTH{1'bx}};
-
-    assign data_to_store = 
-            signals[`CONTROL_MEM_WRITE] ?
-                alu_rr  :
-            {DATA_WIDTH{1'bx}};
+    
+    // TODO incarcati in data_to_store, conform schemei de load
+    always @(posedge clk, posedge reset) begin
+        if (signals[`CONTROL_MEM_WRITE]) begin
+            data_to_store <= alu_rr;
+        end
+        else begin
+            data_to_store <= {DATA_WIDTH{1'bx}};
+        end
+    end
 
     /* Bloc de atribuire al program counter-ului */
     always @(posedge clk, posedge reset) begin
             sreg <= 0;
         else sreg <= alu_flags_out;
 
+    /* Bloc de atribuire al sp-ului */
+    always @(posedge clk, posedge reset) begin
+        if (reset) begin
+            sp <= 0;
+        end
+        else begin
+            if (signals[`CONTROL_POSTDEC]) begin
+                sp <= sp - 8'b1;
+                end
+            else if (signals[`CONTROL_PREINC]) begin
+                sp <= sp + 8'b1;
+                end
+            end
+    end
+
     always @(posedge clk, posedge reset) begin
         if (reset)
             writeback_value <= {DATA_WIDTH{1'b0}};

File decode_unit.v

View file 
                 opcode_imd  = {~instruction[8], instruction[8],
                               instruction[10:9], instruction[3:0]};
             end
-                16'b1000_000?_????_1000: begin
+            16'b1000_000?_????_1000: begin
                 opcode_type = `TYPE_LD_Y;
                 opcode_rd   = instruction[8:4];
                 opcode_rr   = {R_ADDR_WIDTH{1'bx}};
                 opcode_bit  = 3'bx;
                 opcode_imd  = 12'bx;
             end
-                  16'b1010_1???_????_????: begin
+            16'b1010_1???_????_????: begin
                 opcode_type = `TYPE_STS;
                 opcode_rd   = {R_ADDR_WIDTH{1'bx}};
                 opcode_rr   = {1'b1, instruction[7:4]};
                 opcode_imd  = {~instruction[8], instruction[8],
                               instruction[10:9], instruction[3:0]};
             end
-                16'b0010_11??_????_????: begin
+            16'b0010_11??_????_????: begin
                 opcode_type = `TYPE_MOV;
                 opcode_rd   = instruction[8:4];
                 opcode_rr   = {instruction[9], instruction[3:0]};
                 opcode_bit  = 3'bx;
                 opcode_imd  = 12'bx;
             end
-                16'b1100_????_????_????: begin
+            16'b1100_????_????_????: begin
                 opcode_type = `TYPE_RJMP;
                 opcode_rd   = {R_ADDR_WIDTH{1'bx}};
                 opcode_rr   = {R_ADDR_WIDTH{1'bx}};
                 opcode_bit  = 3'bx;
                 opcode_imd  = instruction[11:0];
             end
-                16'b1111_00??_????_?001: begin
+            16'b1111_00??_????_?001: begin
                 opcode_type = `TYPE_BREQ;
                 opcode_rd   = {R_ADDR_WIDTH{1'bx}};
                 opcode_rr   = {R_ADDR_WIDTH{1'bx}};
                 // extend sign bit
                 opcode_imd  = {{5{instruction[9]}}, instruction[9:3]};
             end
-                16'b1111_01??_????_?011: begin
+            16'b1111_01??_????_?011: begin
                 opcode_type = `TYPE_BRVC;
                 opcode_rd   = {R_ADDR_WIDTH{1'bx}};
                 opcode_rr   = {R_ADDR_WIDTH{1'bx}};
                 // extend sign bit
                 opcode_imd  = {{5{instruction[9]}}, instruction[9:3]};
             end
-                16'b1111_00??_????_????: begin
+            16'b1111_00??_????_????: begin
                 opcode_type = `TYPE_BRBS;
                 opcode_rd   = {R_ADDR_WIDTH{1'bx}};
                 opcode_rr   = {R_ADDR_WIDTH{1'bx}};
                 // extend sign bit
                 opcode_imd  = {{5{instruction[9]}}, instruction[9:3]};
             end
-                16'b0001_01??_????_????: begin
+            16'b0001_01??_????_????: begin
                 opcode_type = `TYPE_CP;
                 opcode_rd   = {instruction[8:4]};
                 opcode_rr   = {instruction[9], instruction[3:0]};

File defines.vh

View file 
 `define GROUP_COUNT           14
 `define STAGE_COUNT           3
 `define OPCODE_COUNT          8
-`define SIGNAL_COUNT          6
+`define SIGNAL_COUNT          8
 `define FLAG_COUNT            7
 
 /* Control signals */
 `define CONTROL_REG_RR_WRITE    3
 `define CONTROL_REG_RD_READ     4
 `define CONTROL_REG_RD_WRITE    5
+`define CONTROL_PREINC          6
+`define CONTROL_POSTDEC         7

File schelet.gise

View file 
     <file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
     <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
-    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
     <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="nexys_top.cmd_log"/>
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="nexys_top.lso"/>
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="nexys_top.ngc"/>
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1478000284" xil_pn:in_ck="4335101793248985026" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1478000284">
+    <transform xil_pn:end_ts="1478551561" xil_pn:in_ck="4335101793248985026" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1478551561">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <outfile xil_pn:name="alu.v"/>
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1478000284" xil_pn:in_ck="4335101793248985026" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1478000284">
+    <transform xil_pn:end_ts="1478551561" xil_pn:in_ck="4335101793248985026" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1478551561">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <outfile xil_pn:name="alu.v"/>
       <outfile xil_pn:name="state_machine.v"/>
       <outfile xil_pn:name="test_cpu.v"/>
     </transform>
-    <transform xil_pn:end_ts="1478000287" xil_pn:in_ck="4335101793248985026" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="4902734677147323355" xil_pn:start_ts="1478000284">
+    <transform xil_pn:end_ts="1478551563" xil_pn:in_ck="4335101793248985026" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="4902734677147323355" xil_pn:start_ts="1478551561">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
-      <status xil_pn:value="OutOfDateForOutputs"/>
-      <status xil_pn:value="OutputChanged"/>
       <outfile xil_pn:name="fuse.log"/>
       <outfile xil_pn:name="isim"/>
-      <outfile xil_pn:name="isim.log"/>
       <outfile xil_pn:name="test_cpu_beh.prj"/>
       <outfile xil_pn:name="test_cpu_isim_beh.exe"/>
       <outfile xil_pn:name="xilinxsim.ini"/>
     </transform>
-    <transform xil_pn:end_ts="1478000962" xil_pn:in_ck="5049260449278821244" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-1375619214690815426" xil_pn:start_ts="1478000962">
+    <transform xil_pn:end_ts="1478551563" xil_pn:in_ck="5049260449278821244" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-1375619214690815426" xil_pn:start_ts="1478551563">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
-      <status xil_pn:value="OutOfDateForOutputs"/>
-      <status xil_pn:value="OutputChanged"/>
       <outfile xil_pn:name="isim.cmd"/>
-      <outfile xil_pn:name="isim.log"/>
       <outfile xil_pn:name="test_cpu_isim_beh.wdb"/>
     </transform>
     <transform xil_pn:end_ts="1476060779" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1476060779">